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C/C++ Source or Header  |  2000-05-25  |  19KB  |  507 lines
  1. /***************************************************************************
  2.  
  3. Kick & Run - (c) 1987 Taito
  4.  
  5. Ernesto Corvi
  6. ernesto@imagina.com
  7.  
  8. Notes:
  9. - 4 players mode is not emulated. THis involves some shared RAM and a subboard.
  10.   There is additional code for a third Z80 in the bootleg version, I don't
  11.   know if it's related or if its just a replacement for the 68705.
  12.  
  13. - kicknrun does a PS4 STOP ERROR short after boot, but works afterwards.
  14.   PS4 is the mcu.
  15.  
  16. - kikikai sometimes crashes, might be a synchronization issue
  17.  
  18. ***************************************************************************/
  19.  
  20. #include "driver.h"
  21. #include "cpu/z80/z80.h"
  22.  
  23. /* in machine/mexico86.c */
  24. extern unsigned char *mexico86_protection_ram;
  25. int mexico86_m68705_interrupt(void);
  26. READ_HANDLER( mexico86_68705_portA_r );
  27. WRITE_HANDLER( mexico86_68705_portA_w );
  28. WRITE_HANDLER( mexico86_68705_ddrA_w );
  29. READ_HANDLER( mexico86_68705_portB_r );
  30. WRITE_HANDLER( mexico86_68705_portB_w );
  31. WRITE_HANDLER( mexico86_68705_ddrB_w );
  32.  
  33. /* in vidhrdw/mexico86.c */
  34. extern unsigned char *mexico86_videoram,*mexico86_objectram;
  35. extern size_t mexico86_objectram_size;
  36. void mexico86_vh_convert_color_prom(unsigned char *palette, unsigned short *colortable,const unsigned char *color_prom);
  37. WRITE_HANDLER( mexico86_bankswitch_w );
  38. void mexico86_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
  39. void kikikai_vh_screenrefresh(struct osd_bitmap *bitmap,int full_refresh);
  40.  
  41.  
  42.  
  43. static unsigned char *shared;
  44.  
  45. static READ_HANDLER( shared_r )
  46. {
  47.     return shared[offset];
  48. }
  49.  
  50. static WRITE_HANDLER( shared_w )
  51. {
  52.     shared[offset] = data;
  53. }
  54.  
  55. /*
  56. $f008 - write
  57. bit 7 = ? (unused?)
  58. bit 6 = ? (unused?)
  59. bit 5 = ? (unused?)
  60. bit 4 = ? (usually set in game)
  61. bit 3 = ? (usually set in game)
  62. bit 2 = sound cpu reset line
  63. bit 1 = microcontroller reset line
  64. bit 0 = ? (unused?)
  65. */
  66. static WRITE_HANDLER( mexico86_f008_w )
  67. {
  68.     cpu_set_reset_line(1,(data & 4) ? CLEAR_LINE : ASSERT_LINE);
  69.     cpu_set_reset_line(2,(data & 2) ? CLEAR_LINE : ASSERT_LINE);
  70. }
  71.  
  72.  
  73.  
  74. static struct MemoryReadAddress readmem[] =
  75. {
  76.     { 0x0000, 0x7fff, MRA_ROM },
  77.     { 0x8000, 0xbfff, MRA_BANK1 },    /* banked roms */
  78.     { 0xc000, 0xe7ff, shared_r },    /* shared with sound cpu */
  79.     { 0xe800, 0xe8ff, MRA_RAM },    /* protection ram */
  80.     { 0xe900, 0xefff, MRA_RAM },
  81.     { 0xf010, 0xf010, input_port_5_r },
  82.     { 0xf800, 0xffff, MRA_RAM },    /* communication ram - to connect 4 players's subboard */
  83.     { -1 }  /* end of table */
  84. };
  85.  
  86. static struct MemoryWriteAddress writemem[] =
  87. {
  88.     { 0x0000, 0xbfff, MWA_ROM },
  89.     { 0xc000, 0xe7ff, shared_w, &shared },    /* shared with sound cpu */
  90.     { 0xc000, 0xcfff, MWA_RAM, &mexico86_videoram },
  91.     { 0xd500, 0xd7ff, MWA_RAM, &mexico86_objectram, &mexico86_objectram_size },
  92.     { 0xe800, 0xe8ff, MWA_RAM, &mexico86_protection_ram },    /* shared with mcu */
  93.     { 0xe900, 0xefff, MWA_RAM },
  94.     { 0xf000, 0xf000, mexico86_bankswitch_w },    /* program and gfx ROM banks */
  95.     { 0xf008, 0xf008, mexico86_f008_w },    /* cpu reset lines + other unknown stuff */
  96.     { 0xf018, 0xf018, MWA_NOP },    // watchdog_reset_w },
  97.     { 0xf800, 0xffff, MWA_RAM },    /* communication ram */
  98.     { -1 }  /* end of table */
  99. };
  100.  
  101. static struct MemoryReadAddress sound_readmem[] =
  102. {
  103.     { 0x0000, 0x7fff, MRA_ROM },
  104.     { 0x8000, 0xa7ff, shared_r },
  105.     { 0xa800, 0xbfff, MRA_RAM },
  106.     { 0xc000, 0xc000, YM2203_status_port_0_r },
  107.     { 0xc001, 0xc001, YM2203_read_port_0_r },
  108.     { -1 }  /* end of table */
  109. };
  110.  
  111. static struct MemoryWriteAddress sound_writemem[] =
  112. {
  113.     { 0x0000, 0x7fff, MWA_ROM },
  114.     { 0x8000, 0xa7ff, shared_w },
  115.     { 0xa800, 0xbfff, MWA_RAM },
  116.     { 0xc000, 0xc000, YM2203_control_port_0_w },
  117.     { 0xc001, 0xc001, YM2203_write_port_0_w },
  118.     { -1 }  /* end of table */
  119. };
  120.  
  121. static struct MemoryReadAddress m68705_readmem[] =
  122. {
  123.     { 0x0000, 0x0000, mexico86_68705_portA_r },
  124.     { 0x0001, 0x0001, mexico86_68705_portB_r },
  125.     { 0x0002, 0x0002, input_port_0_r },    /* COIN */
  126.     { 0x0010, 0x007f, MRA_RAM },
  127.     { 0x0080, 0x07ff, MRA_ROM },
  128.     { -1 }    /* end of table */
  129. };
  130.  
  131. static struct MemoryWriteAddress m68705_writemem[] =
  132. {
  133.     { 0x0000, 0x0000, mexico86_68705_portA_w },
  134.     { 0x0001, 0x0001, mexico86_68705_portB_w },
  135.     { 0x0004, 0x0004, mexico86_68705_ddrA_w },
  136.     { 0x0005, 0x0005, mexico86_68705_ddrB_w },
  137.     { 0x000a, 0x000a, MWA_NOP },    /* looks like a bug in the code, writes to */
  138.                                     /* 0x0a (=10dec) instead of 0x10 */
  139.     { 0x0010, 0x007f, MWA_RAM },
  140.     { 0x0080, 0x07ff, MWA_ROM },
  141.     { -1 }    /* end of table */
  142. };
  143.  
  144.  
  145.  
  146. INPUT_PORTS_START( mexico86 )
  147.     PORT_START      /* IN0 */
  148.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
  149.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
  150.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
  151.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
  152.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
  153.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
  154.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
  155.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
  156.  
  157.     PORT_START      /* IN1 */
  158.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER1 )
  159.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER1 )
  160.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER1 )
  161.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
  162.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
  163.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
  164.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
  165.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE )    /* service 2 */
  166.  
  167.     PORT_START      /* IN2 */
  168.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER2 )
  169.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER2 )
  170.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER2 )
  171.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
  172.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
  173.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
  174.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
  175.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
  176.  
  177.     PORT_START
  178.     /* When Bit 1 is On, the machine waits a signal from another one */
  179.     /* Seems like if you can join two cabinets, one as master */
  180.     /* and the other as slave, probably to play four players */
  181.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
  182.     PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
  183.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  184.     PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
  185.     PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
  186.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  187.     PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
  188.     PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
  189.     PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
  190.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  191.     PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) )
  192.     PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) )
  193.     PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
  194.     PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
  195.     PORT_DIPSETTING(    0x20, DEF_STR( 1C_2C ) )
  196.     PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) )
  197.     PORT_DIPSETTING(    0x40, DEF_STR( 2C_1C ) )
  198.     PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) )
  199.     PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
  200.     PORT_DIPSETTING(    0x80, DEF_STR( 1C_2C ) )
  201.  
  202.     PORT_START
  203.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
  204.     PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
  205.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  206.     PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
  207.     PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
  208.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  209.     PORT_DIPNAME( 0x0c, 0x08, "Timer" )
  210.     PORT_DIPSETTING(    0x04, "Slow" )
  211.     PORT_DIPSETTING(    0x08, "Normal" )
  212.     PORT_DIPSETTING(    0x0c, "Fast" )
  213.     PORT_DIPSETTING(    0x00, "Fastest" )
  214.     PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
  215.     PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
  216.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  217.     /* The following dip seems to be related with the first one */
  218.     PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
  219.     PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
  220.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  221.     PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
  222.     PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
  223.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  224.     PORT_DIPNAME( 0x80, 0x80, "Max Players" )
  225.     PORT_DIPSETTING(    0x80, "2" )
  226.     PORT_DIPSETTING(    0x00, "4" )
  227.  
  228.     PORT_START
  229.     /* the following is actually service coin 1 */
  230.     PORT_BITX(0x01, IP_ACTIVE_LOW, IPT_SERVICE, "Advance", KEYCODE_F1, IP_JOY_NONE )
  231.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
  232.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
  233.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
  234.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
  235.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
  236.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
  237.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
  238. INPUT_PORTS_END
  239.  
  240. INPUT_PORTS_START( kikikai )
  241.     PORT_START      /* IN0 */
  242.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
  243.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
  244.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
  245.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
  246.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
  247.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
  248.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
  249.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
  250.  
  251.     PORT_START      /* IN1 */
  252.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY )
  253.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY )
  254.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY )
  255.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
  256.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
  257.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
  258.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
  259.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
  260.  
  261.     PORT_START      /* IN2 */
  262.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_COCKTAIL )
  263.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_COCKTAIL )
  264.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_COCKTAIL )
  265.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
  266.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_COCKTAIL )
  267.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
  268.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
  269.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
  270.  
  271.     PORT_START      /* DSW0 */
  272.     PORT_DIPNAME( 0x01, 0x01, DEF_STR( Cabinet ) )
  273.     PORT_DIPSETTING(    0x01, DEF_STR( Upright ) )
  274.     PORT_DIPSETTING(    0x00, DEF_STR( Cocktail ) )
  275.     PORT_DIPNAME( 0x02, 0x02, DEF_STR( Flip_Screen ) )
  276.     PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
  277.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  278.     PORT_SERVICE( 0x04, IP_ACTIVE_LOW )
  279.     PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
  280.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  281.     PORT_DIPSETTING(    0x08, DEF_STR( On ) )
  282.     PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) )
  283.     PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) )
  284.     PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
  285.     PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
  286.     PORT_DIPSETTING(    0x20, DEF_STR( 1C_2C ) )
  287.     PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) )
  288.     PORT_DIPSETTING(    0x40, DEF_STR( 2C_1C ) )
  289.     PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) )
  290.     PORT_DIPSETTING(    0x00, DEF_STR( 2C_3C ) )
  291.     PORT_DIPSETTING(    0x80, DEF_STR( 1C_2C ) )
  292.  
  293.     PORT_START      /* DSW1 */
  294.     PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
  295.     PORT_DIPSETTING(    0x02, "Easy" )
  296.     PORT_DIPSETTING(    0x03, "Normal" )
  297.     PORT_DIPSETTING(    0x01, "Hard" )
  298.     PORT_DIPSETTING(    0x00, "Hardest" )
  299.     PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )
  300.     PORT_DIPSETTING(    0x00, "50000 100000" )
  301.     PORT_DIPSETTING(    0x0c, "70000 150000" )
  302.     PORT_DIPSETTING(    0x08, "70000 200000" )
  303.     PORT_DIPSETTING(    0x04, "100000 300000" )
  304.     PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )
  305.     PORT_DIPSETTING(    0x00, "2" )
  306.     PORT_DIPSETTING(    0x30, "3" )
  307.     PORT_DIPSETTING(    0x20, "4" )
  308.     PORT_DIPSETTING(    0x10, "5" )
  309.     PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
  310.     PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
  311.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  312.     PORT_DIPNAME( 0x80, 0x80, "Number Match" )
  313.     PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
  314.     PORT_DIPSETTING(    0x00, DEF_STR( On ) )
  315.  
  316.     PORT_START
  317.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 )
  318.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
  319.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_TILT )
  320.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
  321.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
  322.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
  323.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
  324.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
  325. INPUT_PORTS_END
  326.  
  327.  
  328.  
  329. static struct GfxLayout charlayout =
  330. {
  331.     8,8,
  332.     4*2048,
  333.     4,
  334.     { 0x20000*8, 0x20000*8+4, 0, 4 },
  335.     { 3, 2, 1, 0, 8+3, 8+2, 8+1, 8+0 },
  336.     { 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16 },
  337.     16*8
  338. };
  339.  
  340. static struct GfxDecodeInfo gfxdecodeinfo[] =
  341. {
  342.     { REGION_GFX1, 0, &charlayout,   0, 16 },
  343.     { -1 } /* end of array */
  344. };
  345.  
  346.  
  347.  
  348. static struct YM2203interface ym2203_interface =
  349. {
  350.     1,            /* 1 chip */
  351.     3000000,    /* 3 MHz ??? */
  352.     { YM2203_VOL(40,40) },
  353.     { input_port_3_r },
  354.     { input_port_4_r },
  355.     { 0 },
  356.     { 0 }
  357. };
  358.  
  359.  
  360.  
  361. #define MACHINEDRIVER(NAME)                                                         \
  362. static struct MachineDriver machine_driver_##NAME =                                 \
  363. {                                                                                    \
  364.     {                                                                                \
  365.         {                                                                            \
  366.             CPU_Z80,                                                                \
  367.             6000000,        /* 6 MHz??? */                                            \
  368.             readmem,writemem,0,0,                                                    \
  369.             ignore_interrupt,0    /* IRQs are triggered by the 68705 */                \
  370.         },                                                                            \
  371.         {                                                                            \
  372.             CPU_Z80,                                                                \
  373.             6000000,        /* 6 MHz??? */                                            \
  374.             sound_readmem,sound_writemem,0,0,                                        \
  375.             interrupt,1                                                                \
  376.         },                                                                            \
  377.         {                                                                            \
  378.             CPU_M68705,                                                                \
  379.             4000000/2,    /* xtal is 4MHz (????) I think it's divided by 2 internally */    \
  380.             m68705_readmem,m68705_writemem,0,0,                                        \
  381.             mexico86_m68705_interrupt,2                                                \
  382.         }                                                                            \
  383.     },                                                                                \
  384.     60, DEFAULT_60HZ_VBLANK_DURATION,  /* frames per second, vblank duration */        \
  385.     100,    /* 100 CPU slices per frame - an high value to ensure proper */            \
  386.             /* synchronization of the CPUs */                                        \
  387.     0,                                                                                \
  388.                                                                                     \
  389.     /* video hardware */                                                            \
  390.     32*8, 32*8, { 0*8, 32*8-1, 2*8, 30*8-1 },                                        \
  391.     gfxdecodeinfo,                                                                    \
  392.     256, 256,                                                                        \
  393.     mexico86_vh_convert_color_prom,                                                    \
  394.                                                                                     \
  395.     VIDEO_TYPE_RASTER,                                                                \
  396.     0,                                                                                \
  397.     0,                                                                                \
  398.     0,                                                                                \
  399.     NAME##_vh_screenrefresh,                                                        \
  400.                                                                                     \
  401.     /* sound hardware */                                                            \
  402.     0,0,0,0,                                                                        \
  403.     {                                                                                \
  404.         {                                                                            \
  405.             SOUND_YM2203,                                                            \
  406.             &ym2203_interface                                                        \
  407.         }                                                                            \
  408.     }                                                                                \
  409. };
  410.  
  411.  
  412. MACHINEDRIVER( mexico86 )
  413. MACHINEDRIVER( kikikai )
  414.  
  415.  
  416. /***************************************************************************
  417.  
  418.   Game driver(s)
  419.  
  420. ***************************************************************************/
  421.  
  422. ROM_START( kicknrun )
  423.     ROM_REGION( 0x28000, REGION_CPU1 )     /* 196k for code */
  424.     ROM_LOAD( "a87-08.bin", 0x00000, 0x08000, 0x715e1b04 ) /* 1st half, main code         */
  425.     ROM_CONTINUE(           0x20000, 0x08000 )               /* 2nd half, banked at 0x8000 */
  426.     ROM_LOAD( "a87-07.bin", 0x10000, 0x10000, 0x6cb6ebfe ) /* banked at 0x8000             */
  427.  
  428.     ROM_REGION( 0x10000, REGION_CPU2 )     /* 64k for the audio cpu */
  429.     ROM_LOAD( "a87-06.bin", 0x0000, 0x8000, 0x1625b587 )
  430.  
  431.     ROM_REGION( 0x0800, REGION_CPU3 )    /* 2k for the microcontroller */
  432.     ROM_LOAD( "knrmcu.bin",   0x0000, 0x0800, BADCRC(0x8e821fa0) )    /* manually crafted from the Mexico '86 one */
  433.  
  434.     ROM_REGION( 0x40000, REGION_GFX1 | REGIONFLAG_DISPOSE )
  435.     ROM_LOAD( "a87-05.bin", 0x08000, 0x08000, 0x4eee3a8a )
  436.     ROM_CONTINUE(           0x00000, 0x08000 )
  437.     ROM_LOAD( "a87-04.bin", 0x10000, 0x08000, 0x8b438d20 )
  438.     ROM_RELOAD(             0x18000, 0x08000 )
  439.     ROM_LOAD( "a87-03.bin", 0x28000, 0x08000, 0xf42e8a88 )
  440.     ROM_CONTINUE(           0x20000, 0x08000 )
  441.     ROM_LOAD( "a87-02.bin", 0x30000, 0x08000, 0x64f1a85f )
  442.     ROM_RELOAD(             0x38000, 0x08000 )
  443.  
  444.     ROM_REGION( 0x0300, REGION_PROMS )
  445.     ROM_LOAD( "a87-10.bin", 0x0000, 0x0100, 0xbe6eb1f0 )
  446.     ROM_LOAD( "a87-12.bin", 0x0100, 0x0100, 0x3e953444 )
  447.     ROM_LOAD( "a87-11.bin", 0x0200, 0x0100, 0x14f6c28d )
  448. ROM_END
  449.  
  450. ROM_START( mexico86 )
  451.     ROM_REGION( 0x28000, REGION_CPU1 )     /* 196k for code */
  452.     ROM_LOAD( "2_g.bin",    0x00000, 0x08000, 0x2bbfe0fb ) /* 1st half, main code         */
  453.     ROM_CONTINUE(           0x20000, 0x08000 )               /* 2nd half, banked at 0x8000 */
  454.     ROM_LOAD( "1_f.bin",    0x10000, 0x10000, 0x0b93e68e ) /* banked at 0x8000             */
  455.  
  456.     ROM_REGION( 0x10000, REGION_CPU2 )     /* 64k for the audio cpu */
  457.     ROM_LOAD( "a87-06.bin", 0x0000, 0x8000, 0x1625b587 )
  458.  
  459.     ROM_REGION( 0x0800, REGION_CPU3 )    /* 2k for the microcontroller */
  460.     ROM_LOAD( "68_h.bin",   0x0000, 0x0800, 0xff92f816 )
  461.  
  462.     ROM_REGION( 0x40000, REGION_GFX1 | REGIONFLAG_DISPOSE )
  463.     ROM_LOAD( "4_d.bin",    0x08000, 0x08000, 0x57cfdbca )
  464.     ROM_CONTINUE(           0x00000, 0x08000 )
  465.     ROM_LOAD( "5_c.bin",    0x10000, 0x08000, 0xe42fa143 )
  466.     ROM_RELOAD(             0x18000, 0x08000 )
  467.     ROM_LOAD( "6_b.bin",    0x28000, 0x08000, 0xa4607989 )
  468.     ROM_CONTINUE(           0x20000, 0x08000 )
  469.     ROM_LOAD( "7_a.bin",    0x30000, 0x08000, 0x245036b1 )
  470.     ROM_RELOAD(             0x38000, 0x08000 )
  471.  
  472.     ROM_REGION( 0x0300, REGION_PROMS )
  473.     ROM_LOAD( "a87-10.bin", 0x0000, 0x0100, 0xbe6eb1f0 )
  474.     ROM_LOAD( "a87-12.bin", 0x0100, 0x0100, 0x3e953444 )
  475.     ROM_LOAD( "a87-11.bin", 0x0200, 0x0100, 0x14f6c28d )
  476. ROM_END
  477.  
  478. ROM_START( kikikai )
  479.     ROM_REGION( 0x28000, REGION_CPU1 )     /* 196k for code */
  480.     ROM_LOAD( "a85-17.rom", 0x00000, 0x08000, 0xc141d5ab ) /* 1st half, main code         */
  481.     ROM_CONTINUE(           0x20000, 0x08000 )               /* 2nd half, banked at 0x8000 */
  482.     ROM_LOAD( "a85-16.rom", 0x10000, 0x10000, 0x4094d750 ) /* banked at 0x8000             */
  483.  
  484.     ROM_REGION( 0x10000, REGION_CPU2 )     /* 64k for the audio cpu */
  485.     ROM_LOAD( "a85-11.rom", 0x0000, 0x8000, 0xcc3539db )
  486.  
  487.     ROM_REGION( 0x0800, REGION_CPU3 )    /* 2k for the microcontroller */
  488.     ROM_LOAD( "knightb.uc", 0x0000, 0x0800, 0x3cc2bbe4 )
  489.  
  490.     ROM_REGION( 0x40000, REGION_GFX1 | REGIONFLAG_DISPOSE )
  491.     ROM_LOAD( "a85-15.rom", 0x00000, 0x10000, 0xaebc8c32 )
  492.     ROM_LOAD( "a85-14.rom", 0x10000, 0x10000, 0xa9df0453 )
  493.     ROM_LOAD( "a85-13.rom", 0x20000, 0x10000, 0x3eeaf878 )
  494.     ROM_LOAD( "a85-12.rom", 0x30000, 0x10000, 0x91e58067 )
  495.  
  496.     ROM_REGION( 0x0300, REGION_PROMS )
  497.     ROM_LOAD( "a85-08.rom", 0x0000, 0x0100, 0xd15f61a8 )
  498.     ROM_LOAD( "a85-10.rom", 0x0100, 0x0100, 0x8fc3fa86 )
  499.     ROM_LOAD( "a85-09.rom", 0x0200, 0x0100, 0xb931c94d )
  500. ROM_END
  501.  
  502.  
  503.  
  504. GAME( 1986, kicknrun, 0,        mexico86, mexico86, 0, ROT0, "Taito Corporation", "Kick and Run" )
  505. GAME( 1986, mexico86, kicknrun, mexico86, mexico86, 0, ROT0, "bootleg", "Mexico 86" )
  506. GAMEX(1986, kikikai,  0,        kikikai,  kikikai,  0, ROT90, "Taito Corporation", "KiKi KaiKai", GAME_NOT_WORKING )
  507.